3-D Chips: IBM Moves Moore’s Law Into The Third Dimension

-from Science Daily

Science Daily — IBM has announced a breakthrough chip-stacking technology in a manufacturing environment that paves the way for three-dimensional chips that will extend Moore’s Law beyond its expected limits. The technology – called “through-silicon vias” — allows different chip components to be packaged much closer together for faster, smaller, and lower-power systems.

IBM extends Moore’s Law to the third-dimension: An IBM scientist holds a thinned wafer of silicon computer circuits, which is ready for bonding to another circuit wafer, where IBM’s advanced “through-silicon via” process will connect the wafers together by etching thousands of holes through each layer and filling them with metal to create 3-D integrated stacked chips. The IBM breakthrough can shorten wire lengths inside chips up to 1000 times and allow for hundreds more pathways for data to flow among different functions on a chip. This technique will extend Moore’s Law beyond its expected limits, paving the way for a new breed of smaller, faster and lower power chips. (Credit: Image courtesy of IBM Research)

The IBM breakthrough enables the move from horizontal 2-D chip layouts to 3-D chip stacking, which takes chips and memory devices that traditionally sit side by side on a silicon wafer and stacks them together on top of one another. The result is a compact sandwich of components that dramatically reduces the size of the overall chip package and boosts the speed at which data flows among the functions on the chip.

“This breakthrough is a result of more than a decade of pioneering research at IBM,” said Lisa Su, vice president, Semiconductor Research and Development Center, IBM. “This allows us to move 3-D chips from the ‘lab to the fab’ across a range of applications.”

The new IBM method eliminates the need for long-metal wires that connect today’s 2-D chips together, instead relying on through-silicon vias, which are essentially vertical connections etched through the silicon wafer and filled with metal. These vias allow multiple chips to be stacked together, allowing greater amounts of information to be passed between the chips.

The technique shortens the distance information on a chip needs to travel by 1000 times, and allows for the addition of up to 100 times more channels, or pathways, for that information to flow compared to 2-D chips.

IBM is already running chips using the through-silicon via technology in its manufacturing line and will begin making sample chips using this method available to customers in the second half of 2007, with production in 2008. The first application of this through-silicon via technology will be in wireless communications chips that will go into power amplifiers for wireless LAN and cellular applications. 3-D technology will also be applied to a wide range of chips, including those running now in IBM’s high-performance server and supercomputing chips that power the world’s business, government and scientific efforts.

In particular, IBM is applying the new through-silicon-via technique in wireless communications chips, Power processors, Blue Gene supercomputer chips, and in high-bandwidth memory applications:

* 3-D for wireless communications technology: IBM is using through-silicon via technology to improve power efficiency in silicon-germanium based wireless products up to 40 percent, which leads to longer battery life. The through-silicon via technology replaces the wire bonds that are less efficient at transferring signals off of the chip.
* Power Processors explore 3-D for power grid stability: As we increase the number of processor cores on chips, one of the limitations in performance is uniform power delivery to all parts of the chip. This technique puts the power closer to the cores and allows each core to have ample access to that power, increasing processor speed while reducing power consumption up to 20 percent.
* Bringing 3-D stacking to Blue Gene supercomputing and memory arrays: The most advanced version of 3-D chip stacking will allow high-performance chips to be stacked on top of each other, for example processor-on-processor or memory-on-processor. IBM is developing this advanced technology by converting the chip that currently powers the fastest computer in the world, the IBM Blue Gene supercomputer, into a 3-D stacked chip. IBM is also using 3-D technology to fundamentally change the way memory communicates with a microprocessor, by significantly enhancing the data flow between microprocessor and memory. This capability will enable a new generation of supercomputers. A prototype SRAM design using 3-D stacking technology is being fabricated in IBM’s 300 mm production line using 65 nm- node technology.

3-D chip research at IBM

IBM has been researching 3-D stacking technology for more than a decade at the IBM T.J. Watson Research Center and now at its labs around the world. The Defense Advanced Research Projects Agency (DARPA) has supported IBM in the development of tools and techniques for extending chips to the third dimension, with the aim of driving better performance and new applications of chip technologies.

IBM chip breakthroughs

This is the fifth major chip breakthrough in five months from IBM, as it leads the industry in its quest for new materials and architectures to extend Moore’s Law.

In December, IBM announced the first 45nm chips using immersion lithography and ultra-low-K interconnect dielectrics.

In January, IBM announced “high-k metal gate,” which substitutes a new material into a critical portion of the transistor that controls its primary on/off switching function. The material provides superior electrical properties, while allowing the size of the transistor to be shrunk beyond limits being reached today.

In February, IBM revealed a first-of-its-kind, on-chip memory technology that features the fastest access times ever recorded in eDRAM (embedded dynamic random access memory).

Then in March, IBM unveiled a prototype optical transceiver chipset capable of reaching speeds at least eight-times faster than optical components available today.

Note: This story has been adapted from a news release issued by IBM Research.

IBM doubles CPU cooling capabilities with simple manufacturing change

-from ars technica
By Joel Hruska | Published: March 25, 2007 – 10:03PM CT

According to a new paper released at the IEEE Semi-Therm conference, IBM has discovered a way to dramatically improve processor cooling. Unlike some other recent cooling breakthroughs, IBM’s discovery appears to be one that should be relatively inexpensive to implement, and could have a significant impact on consumer microprocessors in the near future. Without fundamentally changing the approach to CPU cooling today and without the use of more advanced setups like water coolers, IBM says that they can double CPU cooling capacity while making it easier and safer to do so.

IBM’s find addresses how thermal paste is typically spread between the face of a chip and the heat spreader that sits directly over the core. Overclockers already know how crucial it is to apply thermal paste the right way: too much, and it causes heat buildup. Too little, and it causes heat buildup. It has to be “just right,” which is why IBM looked to find the best way to get the gooey stuff where it needs to be and in the right amount, and to make it significantly more efficient in the process.

A CPU’s heatspreader is normally attached directly to the core by use of a paste or glue that has been enriched with micrometer-sized ceramic or metal particles. These particles then form heat-evacuation bridges between the core and the cooler, and it’s these bridges that carry heat into the heatspreader.

Diagram: Layers of cooling. (Source: IBM)

In its current form, the process is quite inefficient: IBM’s says that up to 40% of a CPU’s total thermal budget (i.e., the cooling capacity available to draw heat away from the core) is consumed by these particles. This inefficiency is made worse because the particles aren’t truly spread evenly throughout the paste. Instead, particles clump together, forming what IBM refers to as the “Magic Cross”, as shown below at Figure 1. This thickened area is a non-homogeneous mixture of paste and particles that dramatically worsens total cooling efficiency across the core.

Figure 1: the Magic Cross. (Source: IBM)

IBM’s solution was to design a series of micrometer-length trenches into the copper cap that sits above the CPU core, as shown in the top diagram (“hierarchical branched channels”). These larger and smaller trenches allow for paste to be evenly distributed at precisely the points where it would normally pile up and form a Magic Cross-like structure. Utilizing IBM’s new technology allowed researchers to spread thermal paste into a far more homogeneous and efficient pattern, as shown in Figure 2.

Figure 2: Gettin’ groovy. (Source: IBM)

The results are quite impressive. Paste thickness could be reduced by a third, and the pressure required to properly fit a CPU cooler on top of a core was cut in half. All of this, and IBM says that cooling capabilities are effectively doubled.

Manufacturing tools to define the micrometer channels are already in development. IBM offers no specific details on when we might see chips using this new procedure in the wild, but they say that the new technology can be quickly integrated into current manufacturing plants at a low cost and using existing process technologies. Whether or not the AMDs or Intels of the world will buy in remains to be seen, but the potential is undeniable.